a_mythpi
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Hello..
I have certains full custom cells for which I have defined a verilog interface ( just a black box). They have gnd and vdd as input pins. This verilog module is instantiated many times in a higher level verilog module. When i try to generate a flatened gate level netlist using design compiler, the gnd and vdd pins are removed by DC after synthesis. i just wanted to check the scan chain on model sim but I get a lot of warnings abt missing ports( gnd and vdd) and then finally error loading design.
I am sort of confused abt this gnd and vdd pins. Sshould i have gnd and vdd till the top level ? or else how can i solve this problem?
thanks a lot
I have certains full custom cells for which I have defined a verilog interface ( just a black box). They have gnd and vdd as input pins. This verilog module is instantiated many times in a higher level verilog module. When i try to generate a flatened gate level netlist using design compiler, the gnd and vdd pins are removed by DC after synthesis. i just wanted to check the scan chain on model sim but I get a lot of warnings abt missing ports( gnd and vdd) and then finally error loading design.
I am sort of confused abt this gnd and vdd pins. Sshould i have gnd and vdd till the top level ? or else how can i solve this problem?
thanks a lot
