glitch prevention in Power On Reset circuit ??

[cmos_ajay]

I am working on the power on reset (POR) circuit. I used a basic bandgap core to make a ZTAT voltage that is given as a reference to the comparator (-) input. The bandgap core is supplied by VDD which rises very fast. The voltage being monitored is a divided version of VDD. I need to make sure that the bandgap ZTAT voltage comes first and sits at the (-) input of comparator. After that the other comparator input (divided version of VDD) arrives. In other words, I need to 'slowdown' the divided version of VDD. If this is not done, then there will be a glitch in the output of the POR circuit.

How can I do that ? Is there a soft start or some other mechanism ?

Diagrams or technical document will be helpful. Thanks.

 

[dick_freebird]

"backstop" it with some other reference that lights up earlier (like say a resistor
and mos VT, diode, etc.) and make the reference side a pair. Add dV/dt triggered
clamping that covers the fast risetime. Etc. Figure out what's dogging you and
patch it.

 

[cmos_ajay]

Hello dick_freebird, Can you provide some diagram to explain your ideas ? Many Thanks.

 

[leehying]

Generally, you need a bandgap-OK signal generating circuit, and some delay after the bandgap-OK signal, then enable the comparator.

 

[saiaditya]

How about having vbe1 and vbe2+IR to compare? Make sure vbe2 is always less (by having a higher multiplier ratio of the 2 bjt's). So initially when the supply is less, vbe1 will be greater than vbe2 (with I quite small) and as supply increases, I becomes significant and vbe2+IR crosses vbe1. The I and supply threshold can be controlled by resistor division over the bjt's. Ofcourse there could be some delays but night not be significant? Does it help?

 

[leo_o2]

To slow down the VDD divider, a capacitor can be added.

I am working on the power on reset (POR) circuit. I used a basic bandgap core to make a ZTAT voltage that is given as a reference to the comparator (-) input. The bandgap core is supplied by VDD which rises very fast. The voltage being monitored is a divided version of VDD. I need to make sure that the bandgap ZTAT voltage comes first and sits at the (-) input of comparator. After that the other comparator input (divided version of VDD) arrives. In other words, I need to 'slowdown' the divided version of VDD. If this is not done, then there will be a glitch in the output of the POR circuit.

How can I do that ? Is there a soft start or some other mechanism ?

Diagrams or technical document will be helpful. Thanks.

 

[pradeepbadrathwal]

Ajay,
Are you able to find solution for the problem you have stated related with glitch. Can you help me on this.