Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

glitch in the output of digital logic

Status
Not open for further replies.

kickbeer

Full Member level 3
Joined
Nov 7, 2008
Messages
162
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,296
Activity points
2,356
glitch digital logic

Hi,

I've just simulated a folding & interpolating ADC and found a glitch around 0.5 V after an EX-OR logic in my digital part. In the attachment, V(c07) and V(c23) are the input and V(out_07_23) is the output of EX-OR. As you can see in waveform, there is a glitch of 0.5 V(at time 0.3 us) of the output of EX-OR.I'm wondering how this happened because both the inputs travel at the same speed. How to get rid of this problem? I've been working on this since two days.
 

mandar_mahajan

Full Member level 2
Joined
Jul 8, 2009
Messages
134
Helped
7
Reputation
14
Reaction score
5
Trophy points
1,298
Location
mumbai
Activity points
2,090
basics of glitch + digital logic

Dear,
It is very hard to tell u from the w/f's u have posted.
Post ur schematic of circuit on ehich u r working.
Must be a ground related issue.
TRY THIS:
Just check the voltage bet'n main ground & the Analog ground of ADC.
Analog & digital gnd must be different.

Regards
mandar
 

tony_taoyh

Full Member level 2
Joined
Oct 20, 2004
Messages
130
Helped
6
Reputation
12
Reaction score
3
Trophy points
1,298
Activity points
1,777
For the digital logic, you can not assume they are travelling at same speed: process variation, state dependent delay, and so on.

To remove those gritches, you may:
1) Change the method to generate the input signals.
For example, some gray coded counter may help.
2) You may add one latch after the logic.==> idea of sync circuit design.
3) Add enough delay for one of the input. (last solution.)

Hope helpful.
 

    kickbeer

    points: 2
    Helpful Answer Positive Rating

kickbeer

Full Member level 3
Joined
Nov 7, 2008
Messages
162
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,296
Activity points
2,356
mandar_mahajan said:
Dear,
It is very hard to tell u from the w/f's u have posted.
Post ur schematic of circuit on ehich u r working.
Must be a ground related issue.
TRY THIS:
Just check the voltage bet'n main ground & the Analog ground of ADC.
Analog & digital gnd must be different.

Regards
mandar
Hi mandar,

Thanks very much for willing to helpm me.
I wanted to post the schematic but is is too large and may not helpful in solving that problem. Do you have LTSpice? I'll post it if u have so that you can simulate and see yourself more glitches after the digital logic. About the gnd, i think it is integrated in the EX-OR block because i took that directly from LTSpice library. See attachment.
 

mandar_mahajan

Full Member level 2
Joined
Jul 8, 2009
Messages
134
Helped
7
Reputation
14
Reaction score
5
Trophy points
1,298
Location
mumbai
Activity points
2,090
Hi Kickbeer,
Sorry to say but i dont have LTspice & dont know much abt it.
I am not able to understand how ur dealing with ur ckt?
Which ADC u r using?
 

kickbeer

Full Member level 3
Joined
Nov 7, 2008
Messages
162
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,296
Activity points
2,356
mandar_mahajan said:
Hi Kickbeer,
Sorry to say but i dont have LTspice & dont know much abt it.
I am not able to understand how ur dealing with ur ckt?
Which ADC u r using?
LTSpice is a free software form linear technology and it is very easy to use. You can download it from here:

http://www.linear.com/designtools/software/ltspice.jsp

Once you downloaded you can directly run my ADC if you want. Anyway i'm using 8-bit Folding and Interpolating ADC.
 

dick_freebird

Advanced Member level 5
Joined
Mar 4, 2008
Messages
6,961
Helped
2,037
Reputation
4,078
Reaction score
1,883
Trophy points
1,393
Location
USA
Activity points
55,795
I am guessing that with the dual outputs, these are a
CML or SCL logic family.

What I see is that the common-mode voltage of the
two logic inputs you show, is jerked abruptly at a couple
of timepoints. This to me is abnormal and I think maybe
you have some misdefined input signals that are
jacking these gates' operating point (hence timing
and output drive / levels) around.
 

    kickbeer

    points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top