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There are many techniques for it. Depends on you ckt and block.
-For example clock gating is the most command method to minimize the power consumption. Many references available on web about how to implement clk gating.
-Other things like you can use multi VT cells if u are designing an ASIC.
-You can also use bus inversion techniques in some of the cases, where you have to see that bus bits has minimum transition in either normal value or inverted value, and depends on this you have to set a extra bit for that.
-you can use gray state encoding in FMS if possible(all the state transitions are very straight forward i.e. sequence or very few transition from one branch to other.)
- You can encode you state machine such that you will have minimum transitions between the most frequent states.
-Power gating is also there in case you are trageting an ASIC.
there are many others... as of know I can only list out these.
Hope this helps....
The most easy way is to use advanced process. Because core voltage can be reduced, and power is propotional to V square.
Besides, in most SoC design the embedded SRAM is almost the power-hunger monster. The advanced process is more flavor due to its area and power in terms of embedded SRAM,too.
* clock-gating
* power-gating
* multi-Vt libraries (High Vt and low Vt to meet both power and performance, low Vt cells gives high performance high leakage, high Vt gives low performance low leakage power)
* multi -Vdd (Chip with multiple Voltage domains)
* dynamic voltage frequency scaling (DVFS)
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