GHDL & Xilinx - need help

[mlefter]

Hello everyone,

I'm trying to simulate some Xilinx VHDL design with GHDL. Unfortunately I have some problems. I am using GHDL 0.28 and Xilinx Webpack 11.3. Here is how I try to do it.

I got the post-synthesis file - 'temp_synthesis.vhd' which starts like this:
...
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
...

I've copied the 'unisim_VCOMP.vhd' and 'unisim_VPKG.vhd' files from ../Xilinx/11.1/ISE/vhdl/src/unisims into a new created folder. I've added there also the 'temp_synthesis.vhd" and the test bench ('temp_tb.vhd'). I've also created the unisim and work subfolders.

Now the commands that I use:

$ghdl -a --work=unisim --workdir=unisim --ieee=synopsys -fexplicit unisim_VCOMP.vhd
OK

$ghdl -a --work=unisim --workdir=unisim --ieee=synopsys -fexplicit unisim_VPKG.vhd
OK

$ghdl -a --work=work -Punisim --workdir=work --ieee=synopsys -fexplicit temp_synthesis.vhd
OK

$ghdl -a --work=work -Punisim --workdir=work --ieee=synopsys -fexplicit temp_tb.vhd
OK

Here comes the problem. When I do:

$ghdl -m --work=work -Punisim --workdir=work --ieee=synopsys -fexplicit temp_tb

I get a lot of warnings like:
...
temp_synthesis.vhd:56:14:warning: (in default configuration of temp(structure))
temp_synthesis.vhd:5031:3:warning: component instance "so_rout_mask_3_and00001" is not bound
temp_synthesis.vhd:56:14:warning: (in default configuration of temp(structure))
temp_synthesis.vhd:5041:3:warning: component instance "so_rout_mask_2_and00011" is not bound
temp_synthesis.vhd:56:14:warning: (in default configuration of temp(structure))
temp_synthesis.vhd:5051:3:warning: component instance "so_rout_mask_2_and00001" is not bound
temp_synthesis.vhd:56:14:warning: (in default configuration of temp(structure))
...
temp_synthesis.vhd:56:14:warning: (in default configuration of temp(structure))
temp_synthesis.vhd:6745:3:warning: component instance "state_fsm_ffd1_in_sw1" is not bound
...

It looks like no component is bound. What do the warnings mean? Any clue about possible solutions? My objective is to find out whether it's possible to perform timing simulations with GHDL & Xilinx. Can anyone enlighten me?

Thanks,
Mihai

 

[mlefter]

Hello pini_1,

Thanks for the answer. I checked your page but didn't find anything related to post-synthesis or post-map.

Anyway, I discovered the problem. Except for those two files: 'unisim_VCOMP.vhd' and 'unisim_VPKG.vhd" also the 'primitive' folder with all its contents need to be copied. After that the commands:
ghdl -i --work=unisim unisim/*.vhd
ghdl -i --work=unisim unisim/primitive/*.vhd
ghdl -i *.vhd
ghdl -m -g -Punisim --warn-unused --ieee=synopsys temp
ghdl -r temp--wave=temp.ghw

Some warnings still appear but nothing important.

I thank to René Doß from **broken link removed** for that.

Did anybody do some post-map simulations?

Mihai