Navya said:we are planning to have the trace width to be min (12 mils-10 mils).
Is it like we have to decide the core thickness, prepeg distance , copper thickness etc?
Can you briefly explain?and also plz tell it too..
what is meant by base and finish thickness? Plz differentiate
Navya said:Thanks for the help. In our pcn stack up,
The copper base thickness on each layer – 0.5 oz or 0.6693 mils.
Finished copper thickness on each layer – 1.25 oz (i.e. 0.5 oz+ 0.75 oz) or 1.722 mils.
Our pcb board thickness is 5mm
The single ended trace impedance on all signal layers must be a min of 60 ohms and a max of 90 ohms
I'm designing always with 50ohm impedance, but from my experience on short lines (up to 5cm or 2 inch lenght ) there is no problem if the impedance is as high as 60 ohm or 90 ohm if all data lines has the same impedance. On RF lines and high frequency (2.5Ghz or more) is different, line should be kept at 50ohm
There will be +/-10% tolerance in fabrication .So can you please tell the specific value that we should choose for the target impedance?
The 10% tolerance is in the epsilon value (dielectric constant) which shoud be choosed around 4 (3.6 to 4.2) for FR4 material
Also we want to know the thickness of each layer, core thickness, prepeg thickness,trace width, spacing between each trace etc.
Use equal thickness for each layer and prepreg. Trace width is a problem of impedance and current flow. Spacing between traces is a problem of isolation (here there is no such issue because everything is 5V or 3.3V) and crosstalk.
Use larger isolation (greater than 20mil) for routing clocks or data busses.
Separe data busses from analog signals
The minimal route width/isolation is often 4mil for such design. If you have empty space use 8mil or even more.
Plz help asap
Navya said:So can i move forward with a target impedance of 70 ohms?
trace width of 8 mils?
How do you expect I can answer without knowing anything about your schematic ? If you have only 33MHz buses and no RF the answer is yes as long every signal route has the same lenght
we need the help to arrange the prepeg, core inbtween the layers of the stack up (of 20 mils=0.5mm) with the following order(with thickness mentioned in the right side)
On this layer stack I'll keep restictive impedance routes on layer1 and layer4 with a continous ground or power layer under them. Keep supply routes on layer 2 and layer 3 as much as possible. I can't choose for you the layer thickness you are routing so you know the impedance requirement.
layer1-signal/power
layer2-GND
layer3-Signal/power
layer4-signal/power
Can you please provide this information too?
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