Getting layout of a circuit from schematics

[ananish]

cadence layout from schematic

is it possible to get the layout of a circuit using the schematics . i am using tanner .

 

[stober]

help with layout designs

don't know your exact mean but layout xl is useful

 

[bleuame]

helped in layout design

there is not tools for get layout for schmetic in ic design, because the design of layout need a lot of experience, and is an art.

 

[mircea]

Re: help on layout design

you can get the layout from the schematic if you have a digital schematic... called place & route.
usually the analog layout is custom made and you have to do it yourself...

rgds,
M

 

[r_p_sanna]

help on layout design

as far as i know, even to get the layout in digital schematic, we feed the netlist and not the schematic.

 

[mircea]

Re: help on layout design

ones you have the schematic, you can easily get the netlist and then the layout.
works also from vhdl files...

 

[ananish]

Re: help on layout design

ok. is it possible to get the layout from the netlist using tanner eda tool.

 

[centiago]

Re: help on layout design

You can do it any way, not necesarily you need to draw schematic, there are many softwares where you can directly place component on pcb & route as per hand drawn circuit.

Structured approcah is draw schematic & import netlist in PCB. The above mentioned is prone to making error.

 

[selvaraja]

Re: help on layout design

As far as i know in tanner you cant do it for custom analog layout..but in virtuoso cadence hv this features check it out

 

[srijesh]

Re: help on layout design

SDL -Schematic driven layout option is available in a few tools. This could be used in a few digital layouts. Certainly not prefered in Analog Layouts. One major problem in this flow is that you need to flatten out the design if changes are required. If you do that ECO is a pain!

 

[ananish]

Re: help on layout design

can anybody provide the c35b4 manufacturing process.

 

[laglead]

Re: help on layout design

is it possible to get the layout of a circuit using the schematics . i am using tanner .

i don't think so.

 

[ananish]

Re: help on layout design

ok. thank you. i got wrong info regarding the above. thank you very much for clearing my confusion. anybody here working on memory design so that to share our ideas together

 

[vikadik]

Re: help on layout design

There is noway of getting a analog schematic into layout while it is possible in digital using HDL or schematic.

HDL --(Synthesis)--> Gate Netlist --(P&R)--> Layout

 

[p_shinde]

Re: help on layout design

the schematic diagram is used to verify with the drawn layout, its not the thing that we get layout from schematic diagram

for auto place and route too ,after having schematic diagram of ur ckt, we get the netlist from it like .edf format and u get other netlist from the auto place and route of your drawn standard cells.

so then u compare 2 netlists for LVS


same thing for full custom, only change instead of std cells u do complete design urself.

hope this answers ur Q

bye,
Prasad

 

[k.gurunath]

help on layout design

you can get the devices in cadence from the schematic.just drag and drop the devices from schematic window to the layout windows.
and change the properties menu .....
You need to take care of routings........

 

[wells520]

help on layout design

you can get the devices in cadence from the schematic.just drag and drop the devices from schematic window to the layout windows.
and change the properties menu .....
You need to take care of routings........

 

[ersachinkalra]

Re: help on layout design

I am not sure that you can do it through Tanner...but through Virtuoso XL it is very much possible In VXL a Schematic to Layout option is there by which you can invoke the devices from your schematic to your layout canvas..

 

[YESH_23]

help on layout design

laker is also one of this kind

 

[nschutten]

help on layout design

Tanner also supports SDL. When the schematic is completed, and when you have taken care in advance that the layout structures are known in L-edit (e.g. the MOS transistors, resistors, caps, etc. have associated T-cells), then when using SDL, these devices are put in the layout automatically (all correctly sized), with fly-wires that help you indicate how the devices should be interconnected (according to your schematic).