shock369
Newbie level 4
Hi all,
Can anyone explain how design width and length of transistor in this topology or ratio (W/L) of transistor in differential pairs and mirror to get a good matching offset.
Target of design : Design of the low offset (max. 5mV) rail to rail operational amplifier in CMOS technology. OpAmp be use for measurement.
Vdd=5V
Mim. length 0.7 µm
Thanks
Can anyone explain how design width and length of transistor in this topology or ratio (W/L) of transistor in differential pairs and mirror to get a good matching offset.
Target of design : Design of the low offset (max. 5mV) rail to rail operational amplifier in CMOS technology. OpAmp be use for measurement.
Vdd=5V
Mim. length 0.7 µm
Thanks