# Getting either integer or std_logic_vector value to generic. (Or any alternatives)

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#### kaiserschmarren87

##### Member level 4
Hallo,

I have to pass a (6 downto 0) value (it is an output as std_logic_vector) from my top module to one of the sub module(as Generic). Is there any work around for this? (I know that an integer value contained in a signal can't be mapped to a generic variable.

To explain it clearly:

Top module has ------------ sample(6 downto 0);
--Instantiated module ----- count <= to_integer(signed(sample));
----sub_module(pb_debounce shown below) ----------- it has a generic variable named counter which needs the count value to be passed to it since this value comes from configurable memory and it can vary.

I use a similar code:

Code VHDL - [expand]1
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entity pb_debounce is
generic(count : integer)
port(----in/out ports)
);
entity pb_debounce;

architecture behavioral of pb_debounce is
signal SHIFT_PB : std_logic_vector(count-1 downto 0);
begin
process
begin
if rising_edge(clock) then --You're clock

SHIFT_PB(count-2 Downto 0) <= SHIFT_PB(count-1 Downto 1); --Shifting each cycle
SHIFT_PB(count-1) <= NOT PB; --PB is the pre-bounced signal

If SHIFT_PB(count-1 Downto 0)="0000" THEN --once the bounce has settled set the debounced value
PB_DEBOUNCED <= '1';
ELSE
PB_DEBOUNCED <= '0';
End if;
end process;

end behavioral;

I need the shift register to be dependent on varying value of count which is captured from the top module.
I hope the question is clear.

Last edited by a moderator:

#### TrickyDicky

You cant pass a signal as a generic. A generic is a constant at elaboration time thaat is used to set the module up before runtime. Therefore it makes no sense to try and connect a changing signal to it.

kaiserschmarren87

### kaiserschmarren87

Points: 2

##### Super Moderator
Staff member
Besides what Tricky said...
This code...

Code VHDL - [expand]1
signal SHIFT_PB : std_logic_vector(count-1 downto 0);

makes absolutely no sense if the value of count can be modified when in operation (as opposed to during elaboration). That implies that the width of this vector can magically add or subtract the number of bits that are implemented in the design. Dynamic sizing of hardware is impossible, either the hardware exists or it doesn't.

kaiserschmarren87

Points: 2