Hi,
Your question is not clear. There aresome issues:
If your input data rate is 8 bits with 25MHz....and you convert it to 48bit wide..then it is exactely with 4.1667MHz averaged.
You may have burst with 20MHz, but thats a problem of a FIFO buffer.
Are both clocks generated from the same clock source...and therefore they can be considered to be synchronous every 5th/4th clock?
Or are the not synchronous at all.
If not synchronous: Who is generating both clocks and how do you ensure they come to exactely the same data_bit_rate?
Please show a diagram of your data flow with all involved signals.
Klaus