venkyatit
Newbie level 3
Hi. I am new to VHDL. My code appears to be working fine if two variables (defined as integers) are added. It is even working when subtracting (C<=A-B), only if variable A is greater than B.
However, when B is greater than A then the output is incorrect (normally zero), whereas I am looking for a negative output. I tried using signed variables but could n't get my head around it.
Can someone help me?
However, when B is greater than A then the output is incorrect (normally zero), whereas I am looking for a negative output. I tried using signed variables but could n't get my head around it.
Can someone help me?