the following are possible issues:
1.) you have a component with 1 port. It's possible it is an inout port and there is some actual reason for this, but more likely I'm guessing it is a mistake. This does not mean that the design will work if it is an inout port, just that it is the only thing that really would make even the smallest amount of sense, though even that scenario is difficult to believe.
2.) you have if generates inside a for generate which could only have the purpose of allowing 1-3 components to be generated. This seems like a forced use of generate statements that could only make sense if you were trying to determine how generate statement worked despite much easier solutions.
3.) you use "end generate mo" for i0, i1, and i2. this is a syntax error.
4.) you have unmatched parentheses.
5.) I'm not sure if the version of VHDL requires a begin for generates, it might.
it really seems like the entire design could be:
constant wire_a : std_logic_vector(2 downto 0) := "xxx"; -- fill in a value here.
for the generates you could just have a for generate, with adder_a. The select_mode could be set to 2*i+3.
for generates are typically used for duplicated structures, while if-generates are more common with optional functionality.