Generic Functions in Verilog

[dusterman]

Hello All,

First time posting here. I am a student with decent enough FPGA design and VHDL experience but had to learn Verilog 2001 now (and I cant use SystemVerilog) and I was wondering if I can have generic functions in Verilog. This is the kind of thought flow I have gathered till now based on a simple module I want to write now.

module generic_add #(
parameter NUM_IP = 2,
parameter DATA_SIZE = 8
)
(
input wire [NUM_IP*DATA_SIZE-1:0] a, b,
output wire [NUM_IP*DATA_SIZE-1:0] c
)

wire [DATA_SIZE-1:0] a_2d, b_2d [NUM_IP-1:0];
wire [DATA_SIZE-1:0] c_2d [NUM_IP-1:0];
`include "dimensionconversion.v"

assign a_2d = CONVERT_1D_2D (NUM_IP, DATA_SIZE, a); // This is what I want
assign b_2d = CONVERT_1D_2D (NUM_IP, DATA_SIZE, b); // This is what I want
// Say my code here will play with the 2D wires that I got now
// say it will just add the bytes of a and b to give c (ignoring carry)
// in each case
assign c = CONVERT_2D_1D (NUM_IP, DATA_SIZE, c_2d);
endmodule

Now this is what I have got.
1. Verilog 2001 does not support multidimensional ports, so I flatten the multidimensional inputs and outputs to 1-D vector.
2. Within the module, I find it easy to play with 2D vectors and I want to do it in various modules. So the question is how to manage the 1-D to 2-D conversion for inputs and the 2-D to 1-D conversion for outputs.

Option a) I can write a generic function which gives the row, column indices to convert a 1D vector into a 2-D array (and remember the multidimensional indices are parameterized by the calling module).

Option b) Use the part select syntax in Verilog 2001 in each module to select the bytes out of the 1-D vector into a 2-D vector <- Need to update this for each module if the parameter names change.

Now, here are my questions.
1. What would be a better option out of the above 2 options. Is there another option I am missing out on?
2. Right now, option (a) seems appealing to me because I did similar things in VHDL. Is there a way to have generic functions in Verilog or even functions that return multidimensional arrays (that are parameterized in some way)

Thanks and Regards,
Dustin