generic code binary to gray...

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sagar.bavane

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code - vhdl

i am facing problm in making it generic.......

entity gray_count is
generic (
width :INTEGER := 4
);

port( clk : in std_logic;
rst:in std_logic;
enable: in std_logic;
gray: out std_logic_vector(width - 1 downto 0)
);
end gray_count

architecture Behavioral of gray_count is
signal binary : std_logic_vector(width-1 downto 0);
begin
process( clk , rst )
begin
if (rst = '0') then
gray <= (others=>'0');
binary <= (others=>'0');
elsif rising_edge(clk)then
if( enable = '1')then
binary <=binary + '1';
gray <= (binary(width-1) &( binary(width-1 downto 0) xor binary(width-2 downto 0)));------- plz suggest me ulternate to this line.....
end if;
end if;
end process;
end Behavioral;
 


Code: 
[SYNTAX=vhdl]
for i in 0 to width-2 loop
  gray(i) <= binary(i) xor binary(i+1);
end loop;
gray(width-1) <= binary(i+1);
[/SYNTAX]
 
Last edited:

    V

    Points: 2
    Helpful Answer Positive Rating
Code: 
[SYNTAX=vhdl]
function BinToGray (binary : std_logic_vector) return std_logic_vector is
  variable gray : std_logic_vector;
begin
    for i in 0 to binary'length-1 loop
    gray(i) := binary(i) xor binary(i+1);
  end loop;
  gray(binary'length-1) :=binary(binary'length-1);
  return gray;
end function;
[/SYNTAX]

easy way :

Code: 
[SYNTAX=vhdl]
  process( clk , rst )
begin
if (rst = '0') then
  binary <= (others=>'0');
elsif rising_edge(clk) then
  if (enable = '1') then
     binary <=binary + '1';
  end if;
end if;
end process;
----------
gray <= BinToGray(binary);
---------
[/SYNTAX]

better way :

Code: 
[SYNTAX=vhdl]
  process( clk , rst )
begin
if (rst = '0') then
  gray <= (others=>'0');
elsif rising_edge(clk) then
  if (enable = '1') then
     gray <=IncGray(gray)
  end if;
end if;
end process;
[/SYNTAX]

Code: 
[SYNTAX=vhdl]
function IncGray (gray : std_logic_vector) retun std_logic_vector is
 variable var_grey,  var_binaryp, var_binary : std_logic_vector;
begin
  
  var_binary := GrayToBin(gray);
  var_binaryp := var_binary +'1';
  var_gray := BinToGray(var_binaryp);
return var_gray;

end function;  
[/SYNTAX]

Code: 
[SYNTAX=vhdl]
function GrayToBin (gray : std_logic_vector) return std_logic_vector is
  variable var_binary : std_logic_vector;
begin
    for i in binary'length-1 downto 1 loop
      if (gray(i = '0')) then
        var_binary(i-1) := gray(i-1);
     else
        var_binary(i-1) := not gray(i-1);
     end if;
  end loop;
  var_binary(gray'length-1) :=gray(gray'length-1);
  return var_binary;
end function;
[/SYNTAX]

more interesting way : define gray as type gray.
need to define gray package for this and "+" operator.

Code: 
[SYNTAX=vhdl]
signal gray : gray_vector(width-1 downto 0);
[/SYNTAX]

Code: 
[SYNTAX=vhdl]
function "+" (Left : gray_vector, Right: Integer) return gray_vector;

function "+" (Left : gray_vector, Right: Integer) return gray_vector is
variable var_grey,  var_binaryp, var_binary : std_logic_vector;
begin
  var_binary := GrayToBin(Left);
  var_binaryp := var_binary + To_Slv(Right);
  var_gray := BinToGray(var_binaryp);
return var_gray;

end function;  
[/SYNTAX]


Code: 
[SYNTAX=vhdl]
  process( clk , rst )
begin
if (rst = '0') then
  gray <= IntToGray(0, gray'length)
elsif rising_edge(clk) then
  if (enable = '1') then
     gray <=gray+1;
  end if;
end if;
end process;
---------------
[/SYNTAX]
 
Last edited:
Thank U !!!!!!!!!!!!!!
 

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