I'm trying to find a circuit topology for generating fast impulses for a TDR application. The requirement is to generate pulses with about 3.5 V peak amplitude onto a 50 Ω line with pulse widths in the order of 350 ps.
I would be very much grateful if you could shed some light into some circuit topologies I may look into. Also what is the best approach to simulate this sort of circuit?
Normally PECL gates can be configured to produce predictable fast impulses. Consider direct and inverted signal into an OR gate to achieve a pulse 0.8Vpp
Other methods might use a chain of FF's being clocked at 3GHz or ...
a 20GHz 6 bit DAC... or..
an ASIC with a step recovery diode (SRD)