I have a Spartan 6 clocked with 100 MHz (Atlys) and I want to generate the base audio clocks 22.5792 MHz and 24.576 MHz (or some multiple of them). For Fclk/3125 = Fvco/768 I would get Fvco = 24.576 MHz, but this would mean the PLL frequency is 32 KHz. Reading the specs this seems a much to low frequency, both for the VCO and the PLL. Ideas ? :smile:
I have a Spartan 6 clocked with 100 MHz (Atlys) and I want to generate the base audio clocks 22.5792 MHz and 24.576 MHz (or some multiple of them). For Fclk/3125 = Fvco/768 I would get Fvco = 24.576 MHz, but this would mean the PLL frequency is 32 KHz. Reading the specs this seems a much to low frequency, both for the VCO and the PLL. Ideas ? :smile:
Indeed. You're right. The BITCLK is an output in LM4550 primary codec mode, and I should be able to generate the 24.576 MHz clock from it. However I still need the 22.5792 MHz clock, and yet again it seems that the PLL is too limited for this. Ah well, I can always add two external crystal clocks also. No need to force the square peg into the round hole...
Indeed. You're right. The BITCLK is an output in LM4550 primary codec mode, and I should be able to generate the 24.576 MHz clock from it. However I still need the 22.5792 MHz clock, and yet again it seems that the PLL is too limited for this. Ah well, I can always add two external crystal clocks also. No need to force the square peg into the round hole...
Additionally of what aruipksni says, all the multiplications should not exceed 1000 MHz on spartan-6 (values can vary depending of speed grade).
So, in each PLL, you should check if multiplication does not exceed this limit. And yes, DCM was intended for x4 multiplication (but I did not take jitter into account).
I was about to mention the same thing. Yes you can chain pll's, but before you go too far with this in your project best calculate + verify jitter first. That way you can check your favorite datasheets if it's going to be a problem.