Generating base audio clocks with Spartan 6 (PLL?)

[robiwan]

I have a Spartan 6 clocked with 100 MHz (Atlys) and I want to generate the base audio clocks 22.5792 MHz and 24.576 MHz (or some multiple of them). For Fclk/3125 = Fvco/768 I would get Fvco = 24.576 MHz, but this would mean the PLL frequency is 32 KHz. Reading the specs this seems a much to low frequency, both for the VCO and the PLL. Ideas ? :smile:

 

[aruipksni]

I have a Spartan 6 clocked with 100 MHz (Atlys) and I want to generate the base audio clocks 22.5792 MHz and 24.576 MHz (or some multiple of them). For Fclk/3125 = Fvco/768 I would get Fvco = 24.576 MHz, but this would mean the PLL frequency is 32 KHz. Reading the specs this seems a much to low frequency, both for the VCO and the PLL. Ideas ? :smile:

are you syre you need to generate this clock, is it not generated by the AC codec device ?

 

[robiwan]

Yes, I'm sure. The DAC I'm using is the TI PCM4104. I.e. I'm not using the onboard AC codec, this is for driving a prototype board with the PCM4104.

 

[aruipksni]

Yes, I'm sure. The DAC I'm using is the TI PCM4104. I.e. I'm not using the onboard AC codec, this is for driving a prototype board with the PCM4104.

you still can use it (the ac codec' bit_clk) as a system clock, this is the best option,
unless you have other clock sources beside the 100mhz.

 

[robiwan]

you still can use it (the ac codec' bit_clk) as a system clock, this is the best option,
unless you have other clock sources beside the 100mhz.

Indeed. You're right. The BITCLK is an output in LM4550 primary codec mode, and I should be able to generate the 24.576 MHz clock from it. However I still need the 22.5792 MHz clock, and yet again it seems that the PLL is too limited for this. Ah well, I can always add two external crystal clocks also. No need to force the square peg into the round hole...

 

[aruipksni]

Indeed. You're right. The BITCLK is an output in LM4550 primary codec mode, and I should be able to generate the 24.576 MHz clock from it. However I still need the 22.5792 MHz clock, and yet again it seems that the PLL is too limited for this. Ah well, I can always add two external crystal clocks also. No need to force the square peg into the round hole...

you can generate the clock by chaining 3 pll together...

since 100/22.5792 = 7^2*3^2*2^3/5^6 - you can divide it to 3 plls....

 

[pbernardi]

I think if you use 2xPLLs (for each frequency) + DCM you are able to generate 24.576:

PLL1 x8, /25 = 32 MHz, PLL2 x24, /125 = 6.144 MHz (=24576/4)

 

[robiwan]

I think if you use 2xPLLs (for each frequency) + DCM you are able to generate 24.576:

PLL1 x8, /25 = 32 MHz, PLL2 x24, /125 = 6.144 MHz (=24576/4)

Yes, thank you, and with one extra PLL3 x147, /160 = 5.6448 MHz (=22579.2/4). Then 2 DCMs are used to do the final x4 (2*2) ?

 

[aruipksni]

Yes, thank you, and with one extra PLL3 x147, /160 = 5.6448 MHz (=22579.2/4). Then 2 DCMs are used to do the final x4 (2*2) ?

you cannot do this kind of pll divisions in spartan 6 you will need more pll., as i wrote before :

7^2*3^2*2^3/5^6 = 49/25 * 4/25 * 8 /25 = 22579.2

you will need extra pll for the 24.576 calculation.

in any case output jitter levels will be high.

 

[pbernardi]

Additionally of what aruipksni says, all the multiplications should not exceed 1000 MHz on spartan-6 (values can vary depending of speed grade).

So, in each PLL, you should check if multiplication does not exceed this limit. And yes, DCM was intended for x4 multiplication (but I did not take jitter into account).

 

[mrflibble]

in any case output jitter levels will be high.

I was about to mention the same thing. Yes you can chain pll's, but before you go too far with this in your project best calculate + verify jitter first. That way you can check your favorite datasheets if it's going to be a problem.