Generating a pulse signal

[mordak]

Hello,

I have a question about clock generation for testing a chip. I need to test a chip that works with a pulse signal operating at 10 MHZ. This pulse signal needs to be delayed 1 ns every 100 ns. In other words, if first rising edge is at 0 ns, the second one is at 101ns, third rising edge is at 202 ns, and so on.
I wonder how I can generate a pulse like this, I guess no FPGA eval board has that temporal precision (since FPGA clock should be >= 1 GHz).
I appreciate if anyone help me find a solution.

 

[D.A.(Tony)Stewart]

If you are Ok with hardware counters and a 10Mhz clock, you use 2 counters. A counter with a preset of binary value of one hundred and another counter which counts the clock cycles until =0 or the complement counting up to $ff if using a ripple cary out type.

The clock is gated with the count completion to, produce whatever pulse width you need.

At the same time the 2nd counter loads the preset values for the next clock pulse and a latch indicates when done, it shall be incremented once, and the cycle repeats
count preload cycles, preload, imcrement preload the repeat

You can make the ouput pulse any width you want using an XOR gate with an analog RC delay on one side or use gates to get 5us from 10MHz etc etc...

 

[mordak]

If you are Ok with hardware counters and a 10Mhz clock, you use 2 counters.

Thanks for your comment. I don't know if a counter would be a good candidate. I guess there is no off-the-shelf logic IC than can give you a good rise and fall time. I personally haven't seen any logic working at that frequency and having a rise/fall time less than a couple of nano seconds, do you think it would be possible to use logic?
Is there any discrete IC I can use on a PCB that can generate a low jitter clock with the spec I mentioned before?

 

[BigBoss]

It looks like creating PWM.Rising edge is shifted by xns while falling edge is as same as before.
Just an idea..

 

[mordak]

It looks like creating PWM.Rising edge is shifted by xns while falling edge is as same as before.
Just an idea..

Thanks for your post. Actually the whole signal would be shifted by 1 ns, so it is not only the rising edge. In other words, the pulse width would always be constant, and the waveform would be shifted in the time domain by 1 ns.

 

[chuckey]

If the pulse width is constant use a pulse generator for this, if you want the edgges to be 101 nS apart, fire the pulse generator off at a frequency of 1/101 GHZ.
Frank

 

[KlausST]

Hi,

if first rising edge is at 0 ns, the second one is at 101ns, third rising edge is at 202 ns, and so on.

from 0 to 101ns is 101ns,
from 101 to 202 is also 101 ns.

from your description i thought the folowing time should be 102ns.

Please check what you need:
A) 0 (+101) 101 (+101) 202 (+101) 303 (+101) 404...
or
B) 0 (+101) 101 (+102) 203 (+103) 306 (+104) 410 ...

*****
Please specify the timing of the falling edges.

*****
Please specify the upper limit of timing (if distance increases 101, 102, 103...)

*****
With an FPGA and a clock of 1GHz, a counter that counts every ns (1Ghz), a second counter for the TOP value,
and a comparator comparing both counters --> on compare match the GHz counter is reset and the TOP counter is incremented.

*****
Another - not time constant but frequency constant - solution is to work with NCO.
but it decrements frequency: 10.0MHz, 9.9MHz, 9.8MHz, 9.7MHz and so on
This is also possible with FPGAs. But maybe this is even more complicated.

*****

To relax timing, maybe you can live with 100, 100, 102, 102, 104, 104, (2ns steps)

*****
Maybe you can provide more information about your application.

If you need this for ADC undersampling triggering. Then there are better solutions...



Klaus

 

[mordak]

A) 0 (+101) 101 (+101) 202 (+101) 303 (+101) 404...
or
B) 0 (+101) 101 (+102) 203 (+103) 306 (+104) 410 ...

Thanks Klaus!The pattern would be like A. So the timing would be as followings (number in parentheses would be the falling edges) :
0ns (50ns) 101ns (151ns) 202ns (252ns) 303ns ......

With an FPGA and a clock of 1GHz, a counter that counts every ns (1Ghz), a second counter for the TOP value,
and a comparator comparing both counters --> on compare match the GHz counter is reset and the TOP counter is incremented.

Do you know any FPGA eval board that works with an on board clock of 1 GHz? (I don't mean an FPGA IC that can handle that frequency, I mean the evaluation board than works with 1 GHz master clock)

Maybe you can provide more information about your application.

If you need this for ADC undersampling triggering. Then there are better solutions..

Actually I do want it for under sampling, I want to use non uniform sampling and since ADC can't handle high input frequencies I want to employ non-uniform sampling to be able to convert high frequency input signals. I appreciate if you let me know what better solutions are available.

- - - Updated - - -

If the pulse width is constant use a pulse generator for this, if you want the edgges to be 101 nS apart, fire the pulse generator off at a frequency of 1/101 GHZ.
Frank

Hey Frank,
I guess it won't be feasible to use a pulse with 1/101ns frequency. The thing I mentioned was a simple scenario but assume you need to have 10 periods of a pulse with 100 MHz (it should be at 100 MHz), then need to shift the 10 next pulses (again at 100 MHz) by 1ns after the first 10 pulses you had.

 

[KlausST]

Hi,

We use xilinx spartan6. But to be true, i don' t know exactely the upper frequency limit.
But if i remember right we used at least 800MHz, then you have 1.25ns.

Klaus

 

[mordak]

Hi,

We use xilinx spartan6. But to be true, i don' t know exactely the upper frequency limit.
But if i remember right we used at least 800MHz, then you have 1.25ns.

Klaus

The thing is most of the evaluation boards for FPGA I saw work with pretty low frequencies. I wonder if you guys used an eval board with 800MHz or you designed your board.
Besides, you previously mentioned " If you need this for ADC undersampling triggering. Then there are better solutions..." I do need it for under sampling, I appreciate if you let me know what the better solutions are.

 

[KlausST]

Hi,

We use a digilent eval board nexys3 with spartan6.

External clock is 100MHz if i remember right.
But they have internal PLLs, where you can generate higher clock frequencies.
800MHz is possible, i'm sure. I think evev higher.

Better solution
Use two PLLs. One for generating the DUT input clock
One for generating the sample clock.

It is possible to a 10.00MHz clock and a 10.01MHz clock to get a fixed, reliable and stable undersampling rate of 1:1000.
If it is not possible to generate the sample clock from the DUT clock..

In either way the best solution is to generate both clocks with PLLs from a single, common clock. So they have a fixed relation on each other.

Klaus

 

[FvM]

With Altera FPGA, the intended continuously increasing delay can be easily implemented using the PLL dynamic phase shift feature. Phase step resolution is 1/8 of VCO period, e.g. in a 100 ps range. I would expect similar features for Xilinx FPGAs.