generate higher frequencies at the output using fpga

[Pallavipatil]

i m doing this project(part of my curriculum) which needs me to generate frequencies higher than the system clk using the propagation delays in fpga devices. I'm new to this technology so can anyone please guide me as to how to go about doing this project. I searched on the net and came across this DLL technique. Dont know if it is right, but if it is can anyone pls let me know about how the circuit design should be. I have to use ISE tool for this implementation which is again new for me. Thanks in advance.

 

[shitansh]

i m doing this project(part of my curriculum) which needs me to generate frequencies higher than the system clk using the propagation delays in fpga devices.

HI,

First look at user guide of kit you are going to use (eg. sparten3n or any xilinx kit) from that you will get information about if that kit has PLL module or not and if yes then how may?

By using of PLL you can able to generate higher frequency at output.

I have to use ISE tool for this implementation which is again new for me.

I hope this book help you as bigginer to ISE and FPGA.

https://depositfiles.com/en/files/8407456

This is FPGA Prototyping Using Verilog Examples Sparten3 Version.

 

[goshka]

https://www.xilinx.com/support/documentation/application_notes/xapp132.pdf

 

[Pallavipatil]

Hi, Thanks for your help. So PLL it is, right? and how about DLL, what is it used for then. And just in case if the kit does not support PLL module then what?

 

[shitansh]

how about DLL, what is it used for then. And just in case if the kit does not support PLL module then what?

Hi
Dll used for application like high speed ADC with tollarable jitter.
If in case your kit does not have PLL then you have to write RTL code for CLK multipler.

--

 

[kvingle]

Which is the FPGA you are targeting to?

 

[tlp71@hotmail.com]

some devices ,lattice, actel surely have a dedicated analog pll inside the device.
you can use this .

 

[Pallavipatil]

Actually I will be doing this project as a part of my Masters curriculum. Have no idea at all about what FPGA is. Have to generate high frequencies using propagation delay. My prof has advised me to use DCM and not PLL/DLL as these generate clock skew. Again I dont know how to use DCM to generate propagation delay and in turn high frequencies. can anyone pls guide me on this?

 

[kvingle]

Your professor sounds reasonable.

DCM is an acronym for Digital Clock manager .

It is a resource available in FPGAs from Xilinx.

As you are saying you are new to FPGAs. First you need to learn basics of FPGA, and a HDL(such as VHDL or VERILOG)
Then you can do the desired task using reference given by xilinx here.




documentation is also available in your local xilinx installation directory.

 

[Pallavipatil]

Thanks for ur help. Do I have to implement this using some circuit as in adder, multiplier, etc. or is there any other simpler way to do this. Or just selecting the options in the ISE tools' DCM wizard would be enough.

 

[kvingle]

DCM wizard.
Yes you can use that.
you don't need any adder /multiplier refer to DCM docs.