Generate a SAIF file using Verilog RTL simulation

[scholin]

as title, i want to generate a saif file using verilog rtl simulation.
but when i run the command, the terminal shows the error message as belows:
$set_toggle_region(test.dut1);
|
ncelab: *E,NOTSYT (./rtlsim.pat, 127|21): Unrecongnied system task or function (did not math built-in or user-defined names) [2.7.4 (IEE Std 1364-2001)].
If item was defined in a shared-object library, the problem could be:
libvpi.so: cannot open share object file: No such file or directory.
$toggle_start();
|
ncelab: *E,NOTSYT (./rtlsim.pat, 128|16): Unrecongnied system task or function (did not math built-in or user-defined names) [2.7.4 (IEE Std 1364-2001)].
$toggle_stop();
|
ncelab: *E,NOTSYT (./rtlsim.pat, 132|15): Unrecongnied system task or function (did not math built-in or user-defined names) [2.7.4 (IEE Std 1364-2001)].
$toggle_report("Mode_4_saif", 1.0e-12, "test");
|
ncelab: *E,NOTSYT (./rtlsim.pat, 133|17): Unrecongnied system task or function (did not math built-in or user-defined names) [2.7.4 (IEE Std 1364-2001)].


I have found the libvpi.so file and added the path in .cshrc.
but when i run the command again, the terminal shows the error message again.
who can tell me why?

any one can help me?
Thanks!!