Re: some digital Q? ans it
1. What is setup/hold time and metastability?
Ans: Set up time is the minimum time for an input for a syncronous circuit to remain constant before the clock edge traniston. Hold time is the minimum time for the input to remain constant after the clock edge transition. If these two conditions are not met, this will lead to metastability which is an unknown state.
2. How to interconnect two synchronous digital design with different clock domains?or How to connect asynchronous external signal to synchronous design?
Ans: You have to do a clock recovery. Normally people use a clock recovery circuit in the form of DLL/PLL. This will ensure that the data is transferred synchronously to the next clock domain
3. What is DFT?
DFT is design for testability
4. Whal is logic race?
Logic race condition exists when, two mutually-exclusive events are simultaneously initiated through different circuit elements by a single cause, failing the predictability. For example when Q and QB(Q and QB are mutually exclusive) in a SR NAND type Latch are forced to '1' by the SR inputs when they turn to "0" at the same time. Hence we tend to add some delay between one of the outputs, so that the other output wins.