General questions in the field of digital design

[abhineet22]

some digital Q? ans it

1. What is setup/hold time and metastability?
2. How to interconnect two synchronous digital design with different clock domains?
or How to connect asynchronous external signal to synchronous design?
3. What is DFT?
4. Whal is logic race?

 

[GroundCtrl]

Re: some digital Q? ans it

ha-ha-ha...
I writed these questions on ASIC board only for interwivers? Are you asked these questions in job interview?

 

[Vamsi Mocherla]

Re: some digital Q? ans it

1. What is setup/hold time and metastability?
Ans: Set up time is the minimum time for an input for a syncronous circuit to remain constant before the clock edge traniston. Hold time is the minimum time for the input to remain constant after the clock edge transition. If these two conditions are not met, this will lead to metastability which is an unknown state.

2. How to interconnect two synchronous digital design with different clock domains?or How to connect asynchronous external signal to synchronous design?
Ans: You have to do a clock recovery. Normally people use a clock recovery circuit in the form of DLL/PLL. This will ensure that the data is transferred synchronously to the next clock domain

3. What is DFT?
DFT is design for testability

4. Whal is logic race?
Logic race condition exists when, two mutually-exclusive events are simultaneously initiated through different circuit elements by a single cause, failing the predictability. For example when Q and QB(Q and QB are mutually exclusive) in a SR NAND type Latch are forced to '1' by the SR inputs when they turn to "0" at the same time. Hence we tend to add some delay between one of the outputs, so that the other output wins.

 

[GroundCtrl]

Re: some digital Q? ans it

2. How to interconnect two synchronous digital design with different clock domains?or How to connect asynchronous external signal to synchronous design?
Ans: You have to do a clock recovery. Normally people use a clock recovery circuit in the form of DLL/PLL. This will ensure that the data is transferred synchronously to the next clock domain


Normal people live simly ) Trigger chain is simplest solution of this problem.

 

[AlexWan]

Re: some digital Q? ans it

Hi,

About Question 2, Please refer the paper wrote by Clifford E.Cumming.
<Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs> SNUG San Jose 2001

You could get it from Comming's web-site:
http://www.sunburst-design.com/papers/

Good Luck

 

[tutx]

Re: some digital Q? ans it

3. DFT (Design for testability) is a method that add some additional logics in order to increase testability. In other words, a method of adding some additional logics to ease testing the circuit.

 

[jas_bakshi]

Re: some digital Q? ans it

setup time = time for which ur input should be stable so that clock can detect it.
hold time = time after the clcok edge till which output should be stable.

Metastability is the phenomenon in which the state of the output cannot be detected due to the setup or hold violation.This occurs mainly in clock domain crossing.

DFT is design for test.

For connecting 2 sync designs with different clocks u can use double level synchronizer......so that MTBF is met.

 

[spauls]

Re: some digital Q? ans it

dear jas_baksi
i disagree with you

Metastability is the phenomenon in which the state of the output cannot be detected due to the setup or hold violation.This occurs mainly in clock domain crossing.

Metastability can also occur without clock domain crossing , say for high fanout networks .

For connecting 2 sync designs with different clocks u can use double level synchronizer......so that MTBF is met

MTBF is related to sync life not to timing .

 

[jas_bakshi]

Re: some digital Q? ans it

thanks Mr. spauls for correcting me.Ur support will be appreciated in the future.

 

[eeeraghu]

Re: some digital Q? ans it

When We are connecting two different blocks of different clock domains, Here is the situation where the setup and hold time violations occur, so care should be taken that there arises no metastability condition. U can use a flip flop delaybetween the interconnect in order to avoid metastability. or two or three.

so my another question would be are setup and holtime violations possible in a single clock domain circuit.
Please look into this and reply

 

[manik_vivek_82]

Re: some digital Q? ans it

Design for testability is viewing the difficulties of testing during design phase and designing hardware for it..