General Question on Transistor Sizing

[npsnpsnps]

This is a general question on sizing of transistors. I would like to know if there is any generalized way to start designing a circuit (deciding on transistor sizes) for all the applications. I know the length is same and depends on technology. But how to adjust the width ? Does the sizing or the W/L ratio depend only on the circuit I am designing or is there any general flow or starting point for this ? Any tutorials or documents or key points to keep in mind when sizing a huge circuit with lot of transistors would be helpful (key points for example - When designing NAND or NOR, Inverter is taken as reference)

 

[BigBoss]

W/L ratio problem is essentially more complex than you can imagine.Because this ratio impacts many operating specifications of the transistor such as noise,linearity,speed,thermal issues etc.
Therefore this is a compromising problem rather than simply choosing a W/L ratio.Depends also on the process which you intend to use.

 

[npsnpsnps]

Adding to my OP, what are the key points to be considered while sizing when I go down the technology. For example a transistor has W/L = 4 for 180nm technology (W=720nm and L=180nm). If I want to design in 45nm, should I increase the width by 4 to 128nm or increase it further as the technology has scaled down by a large margin.

 

[dick_freebird]

For digital everything will be minimum L (provided
you agree with the foundry's "use model" that
underpins the reliability assessment). In some
cases you might (say) bump the NMOS L to rough
match min-L PMOS strength at equal width.

Width is for drive strength, and the required drive
is unknown for a custom analog block, or set by
some user:developer chest-bumping in library
development. I have commonly seen a series of
min-W (what sets min, varies) gates plus drive
strength increments.

Min-w could be set by AA lithiography minimum,
by contact-to-AA, or larger by interests such as
minimum of 2 contacts per region (for yield /
reliability) or a desire to have a routable lane
between one S and one D contact in larger,
silicide strapped S/D regions (min W is then about
3-4 X litho min, consisting of 3 contact, 6 oversize
and 2 metal spacing).

There are flavors of logic library (speed, density, power)
and there will be different width-trades taken. Rules of
thumb that are generally and consistently useful, I am
not so optimistic - certainly unwilling to trust any over
my own param-fiddling and use-test-cases.

 

[rmanalo]

There's a "digital mindset" in the question itself. A starting point for general digital design: it's best to use minmum lenths and adjust the widths to match the nMOS and pMOS transistors.
For analog design, however, it's much more complex as post #2 stated and difficult to summarize in a single post. But books and tutorials are available. There are documentations on student design projects posted here as a reference: https://cmosedu.com/jbaker/students/students.htm under the students section.