For digital everything will be minimum L (provided
you agree with the foundry's "use model" that
underpins the reliability assessment). In some
cases you might (say) bump the NMOS L to rough
match min-L PMOS strength at equal width.
Width is for drive strength, and the required drive
is unknown for a custom analog block, or set by
some user:developer chest-bumping in library
development. I have commonly seen a series of
min-W (what sets min, varies) gates plus drive
strength increments.
Min-w could be set by AA lithiography minimum,
by contact-to-AA, or larger by interests such as
minimum of 2 contacts per region (for yield /
reliability) or a desire to have a routable lane
between one S and one D contact in larger,
silicide strapped S/D regions (min W is then about
3-4 X litho min, consisting of 3 contact, 6 oversize
and 2 metal spacing).
There are flavors of logic library (speed, density, power)
and there will be different width-trades taken. Rules of
thumb that are generally and consistently useful, I am
not so optimistic - certainly unwilling to trust any over
my own param-fiddling and use-test-cases.