General FPGA VHDL syncronous design question

[automatic]

I am struggling with some synchronous design issues.
Imagine I have a process where I create a single cycle "tick" (e.g. a synchronized wr signal from a CPU) which is one clock cyle.
If my system is clocked at the rising edge this tick goes high just after the rising edge and goes low just after the next rising edge.

If I use this "tick" in another process f.i. to strobe data at the rising clock edge, I more or less rely on the fact the the data is still on the output of the previous flip flop and does not immediately goes low on the rising clock.
I wonder if this is a common way to do.

e.g. "tick" is a single clock cycle pulse.

process strobe
if rising_edge(clk) then

if tick = '1' then​

Data_read <= DB​

else​

Data_read <= (others '0')​

end if;​

end if;

Imagine that tick goes high at rising edge 1 and goed low at rising edge 2
In the strobe process tick usually still has the '1' value at rising edge 2

But it feels to me as reading in the "margin", so is this a good practice or are there other ways ?

 

[lucbra]

you will actually have two delays:
one from the clk to tick and
one delay from the tick to data

This is quite common way to implement this 'data enable'

 

[permute]

It sounds like you are just describing "hold time". the tools should be checking for hold time violations if things are done correctly.