dadda007
Newbie level 5
external trigger vhdl
I have been trying to develop a hardware model for generating a clock pulse of 1 micro-seconds duration at the ocurance of a trigger signal. I have 2 input signals one , the clock signal and another one is the trigger signal. The output signal is the 1 micro-second pulse. For the implementation of the same I used the following method:
1) Use a D-Flipflop which takes clock signal(period less than 1 us) as the clock input and trigger signal as the input for the 'D' pin.
2) At the output of the q-bar we use a delay unit of 1 us. The output of the q-bar output is then put into the input of the 2 input AND gate , with the other input being the output 'q' of the d-flipflop.
The idea of such a model is that as the trigger pulse goes from low to high the q-bar output goes high to low and when the q-bar output is passed through delay unit , we get a shifted q-bar pulse. When we AND q and q-bar output , the expected output is a 1-us pulse.
I wrote the following code in VHDL but it did not give the desired output.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity pulse is
port(
ack : in BIT;
clk : in BIT;
pulse : out BIT);
end entity pulse;
architecture pulse_behav of pulse is
signal q,qbar,d,qbar_delay;
begin
process(clk)
begin
d<=ack;
if(clk'event and clk='1') then
q<=d;
end if;
qbar_delay<=transfer qbar after 1 us;
pulse<=q and qbar;
end process;
end pulse_behav;
I am a new newbie and need help
:!:
I have been trying to develop a hardware model for generating a clock pulse of 1 micro-seconds duration at the ocurance of a trigger signal. I have 2 input signals one , the clock signal and another one is the trigger signal. The output signal is the 1 micro-second pulse. For the implementation of the same I used the following method:
1) Use a D-Flipflop which takes clock signal(period less than 1 us) as the clock input and trigger signal as the input for the 'D' pin.
2) At the output of the q-bar we use a delay unit of 1 us. The output of the q-bar output is then put into the input of the 2 input AND gate , with the other input being the output 'q' of the d-flipflop.
The idea of such a model is that as the trigger pulse goes from low to high the q-bar output goes high to low and when the q-bar output is passed through delay unit , we get a shifted q-bar pulse. When we AND q and q-bar output , the expected output is a 1-us pulse.
I wrote the following code in VHDL but it did not give the desired output.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity pulse is
port(
ack : in BIT;
clk : in BIT;
pulse : out BIT);
end entity pulse;
architecture pulse_behav of pulse is
signal q,qbar,d,qbar_delay;
begin
process(clk)
begin
d<=ack;
if(clk'event and clk='1') then
q<=d;
end if;
qbar_delay<=transfer qbar after 1 us;
pulse<=q and qbar;
end process;
end pulse_behav;
I am a new newbie and need help
:!: