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Geneating a clock pulse at an external trigger signal

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dadda007

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external trigger vhdl

I have been trying to develop a hardware model for generating a clock pulse of 1 micro-seconds duration at the ocurance of a trigger signal. I have 2 input signals one , the clock signal and another one is the trigger signal. The output signal is the 1 micro-second pulse. For the implementation of the same I used the following method:

1) Use a D-Flipflop which takes clock signal(period less than 1 us) as the clock input and trigger signal as the input for the 'D' pin.

2) At the output of the q-bar we use a delay unit of 1 us. The output of the q-bar output is then put into the input of the 2 input AND gate , with the other input being the output 'q' of the d-flipflop.

The idea of such a model is that as the trigger pulse goes from low to high the q-bar output goes high to low and when the q-bar output is passed through delay unit , we get a shifted q-bar pulse. When we AND q and q-bar output , the expected output is a 1-us pulse.

I wrote the following code in VHDL but it did not give the desired output.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity pulse is

port(
ack : in BIT;
clk : in BIT;
pulse : out BIT);

end entity pulse;

architecture pulse_behav of pulse is

signal q,qbar,d,qbar_delay;

begin

process(clk)

begin

d<=ack;

if(clk'event and clk='1') then
q<=d;
end if;

qbar_delay<=transfer qbar after 1 us;
pulse<=q and qbar;

end process;

end pulse_behav;


I am a new newbie and need help
:!:
 

j_andr

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vhdl trigger two pulses

1. d<=ack and q<=d
you do not have to follow 'architecture' of ttl 7474,
q<=ack should work;
2. there is no assignment to qbar - seems you assume
the compiler will recognize what to do with qbar just from the name;
3. if you repair qbar your design would eventually work
in a simulator, but not in an fpga;
qbar_delay<=transfer qbar after 1 us <- there is
no hardware inside fpga to realize transfer after;
the only way to measure time in a pure digital circuit is counting
slopes of a periodical signal of known period [clock];
at least if the delay is bigger then several nanoseconds;
so you should have a clock connected to your hardware which
runs a counter, a trigger signal which enables counting, logic
which can recognize the counter value corresponding to your
desired pulse length;
---
 

lucbra

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Hello,

If you design the pulse to be synthesisable, then you will need to count a number of clock cylces, like j_andr wrote before.

so the process will look like:
process (ack)
begin
if Reset then
pulse <= '0';
elsif rising_edge(clk) then
if ack = '1' then
if count <= number_of_pulses_needed_for_1us then
pulse <= '1';
else
pulse <= '0';
end if;
if count = max_count then
count <= 0;
else
count <= count + 1;
end if;
end process;

Up to you to declare the neccessary signals and work it out in detail.
If you find this code fits your need, you can always donate.
thanks
 

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