As the snippet of code shown above, I am wondering if it's a good practice to perform logic operation on rst signal. rst signal is a global reset signal. if not, how can i modify the code.
this is bad coding style. reset should not be treated as logic, it is a special signal after all. if you follow a traditional template for sequential logic you can avoid this:
Code:
always @(posedge clk) begin
if (reset)
counter <= load_value;
else begin
if (reload)
counter <= load_value;
else
counter <= counter + 1;
end
end
this is bad coding style. reset should not be treated as logic, it is a special signal after all. if you follow a traditional template for sequential logic you can avoid this:
Code:
always @(posedge clk) begin
if (reset)
counter <= load_value;
else begin
if (reload)
counter <= load_value;
else
counter <= counter + 1;
end
end
Unless load_value is a constant, this is only slightly better as reset is still being treated as a logic input (i.e. it is another load enable).
The reset should set the counter to a constant e.g.: (others => '0'), (others => '1'), or some constant value. Using a constant will ensure any dedicated reset resources will be used in the design and not merged into the general purpose logic cells.
For most FPGA families, an asynchronous global reset is available without consuming additional logic resources, not a synchronous reset as shown above.
Unless load_value is a constant, this is only slightly better as reset is still being treated as a logic input (i.e. it is another load enable).
The reset should set the counter to a constant e.g.: (others => '0'), (others => '1'), or some constant value. Using a constant will ensure any dedicated reset resources will be used in the design and not merged into the general purpose logic cells.
this is bad coding style. reset should not be treated as logic, it is a special signal after all. if you follow a traditional template for sequential logic you can avoid this:
Code:
always @(posedge clk) begin
if (reset)
counter <= load_value;
else begin
if (reload)
counter <= load_value;
else
counter <= counter + 1;
end
end
Thanks for your answer. Now, I want to consider a similar circuit where I keep reload signal and remove reset signal. If the reload signal is a control signal generated by a FSM. Will it infer a FDRE with reset port connected to 0, while D is connected to a MUX with reload signal acting as a sel signal?
For most FPGA families, an asynchronous global reset is available without consuming additional logic resources, not a synchronous reset as shown above.
Unless load_value is a constant, this is only slightly better as reset is still being treated as a logic input (i.e. it is another load enable).
The reset should set the counter to a constant e.g.: (others => '0'), (others => '1'), or some constant value. Using a constant will ensure any dedicated reset resources will be used in the design and not merged into the general purpose logic