Gating clock problem_How to avoid glitch?

[lunren]

Dear all,

I want to design a gating clock circuitry which select one clock from two asynchrous clocks. There is possilbe to generate glitch during switching from one clock to the other. How can I suprress this possible clock glitch? Thanks in advance.

Lunren

 

[johnkelvin]

you can get a gate signal A, which is lanched by the falling edge of the clock. Then ~A & clock can stop the clock.
Then use a gate signal B, which is lanched by the rising edge of the clock. Then B & clock can renew the clock.

 

[shankarmit]

can u explain more about this concept to avoid clock gating.

Regards
Shankar

 

[matthew_wang]

the method johnkelvin mentioned is used to avoid glitch for single clock gated.

But this method can also be used, you can first select one clock use mux, and then use the selected clock and its enable signal to synthesize the output clock

 

[yuenkit]

put a latch at the gating signal

 

[xv_ning999]

please upload some picture to help explain it

 

[xihushui]

i also need some presentation about the topic.cound you give more explanation!

 

[xv_ning999]

https://www.us.design-reuse.com/articles/article5827.html

refer to this article

 

[richardhuang]

Using Clock gating must be handled carefully.
you may get the function by RTL code,but the
professional method is done by full custom instead
of synthesis from RTL

 

[artem]

i guess smooth transition from one freq to another can be done with pll . Or glitch impact can be reduced if freq divided and multiplied again .

 

[AlexWan]

For my opinion, xv_ning999 is right. If you want to get the clock with glitch free, you have to pay more cost. Maybe add four flip-flop is a good choice.

 

[eternal_nan]

The following link has the circuit you need:

**broken link removed**

 

[spauls]

Did u try running power compiler.

 

[navi_s]

Hello
Here is verilog file with ClockMux implemented.

//************************************************************
//Clock multiplexer
//------------------------------------------------------------
// if SCK1 is high then clock output = CKO else output = CK1
//************************************************************
`timescale 1ns/1ns
module CKMUX(
CK0,
CK1,
PORB,
SCK1,
CKO
);
// Internal Declarations

input CK0;
input CK1;
input PORB;
input SCK1;
output CKO;


wire CK0;
wire CK1;
wire PORB;
wire SCK1;
reg CKO;
wire RESB0;
reg OUTFR0, OUTFF0;
reg OUTMUX0;
wire RESB1;
reg OUTFR1, OUTFF1;
reg OUTMUX1;
wire RS, SEL;

// RESB0
assign RESB0 = PORB & ~SCK1;

// dfrrl0
always @ (posedge CK0 or negedge RESB0)
begin
if (!RESB0)
OUTFR0 <= 0;
else
OUTFR0 <= RESB0;
end

// dffrl0
always @ (negedge CK0 or negedge RESB0)
begin
if (!RESB0)
OUTFF0 <= 0;
else
OUTFF0 <= RESB0;
end

// mux inverted out0
always @ (CK1 or OUTFR0 or OUTFF0)
begin
case (CK1)
0 : OUTMUX0 = ~OUTFR0;
1 : OUTMUX0 = ~OUTFF0;
// default : OUTMUX0 = ~OUTFR0;
endcase
end

// RESB1
assign RESB1 = PORB & SCK1;

// dfrrl1
always @ (posedge CK1 or negedge RESB1)
begin
if (!RESB1)
OUTFR1 <= 0;
else
OUTFR1 <= RESB1;
end

// dffrl1
always @ (negedge CK1 or negedge RESB1)
begin
if (!RESB1)
OUTFF1 <= 0;
else
OUTFF1 <= RESB1;
end

// mux inverted out0
always @ (CK0 or OUTFR1 or OUTFF1)
begin
case (CK0)
0 : OUTMUX1 = ~OUTFR1;
1 : OUTMUX1 = ~OUTFF1;
// default : OUTMUX1 = ~OUTFR1;
endcase
end

// RS
assign RS = ~(OUTMUX0 & SEL);
// SEL
assign SEL = ~(RS & OUTMUX1 & PORB);

// mux out clock
always @ (CK0 or CK1 or SEL)
begin
case (SEL)
0 : CKO = CK0;
1 : CKO = CK1;
// default : CKO = CK1;
endcase
end
endmodule