lunren
Member level 4
Dear all,
I want to design a gating clock circuitry which select one clock from two asynchrous clocks. There is possilbe to generate glitch during switching from one clock to the other. How can I suprress this possible clock glitch? Thanks in advance.
Lunren
I want to design a gating clock circuitry which select one clock from two asynchrous clocks. There is possilbe to generate glitch during switching from one clock to the other. How can I suprress this possible clock glitch? Thanks in advance.
Lunren