Hello
Here is verilog file with ClockMux implemented.
//************************************************************
//Clock multiplexer
//------------------------------------------------------------
// if SCK1 is high then clock output = CKO else output = CK1
//************************************************************
`timescale 1ns/1ns
module CKMUX(
CK0,
CK1,
PORB,
SCK1,
CKO
);
// Internal Declarations
input CK0;
input CK1;
input PORB;
input SCK1;
output CKO;
wire CK0;
wire CK1;
wire PORB;
wire SCK1;
reg CKO;
wire RESB0;
reg OUTFR0, OUTFF0;
reg OUTMUX0;
wire RESB1;
reg OUTFR1, OUTFF1;
reg OUTMUX1;
wire RS, SEL;
// RESB0
assign RESB0 = PORB & ~SCK1;
// dfrrl0
always @ (posedge CK0 or negedge RESB0)
begin
if (!RESB0)
OUTFR0 <= 0;
else
OUTFR0 <= RESB0;
end
// dffrl0
always @ (negedge CK0 or negedge RESB0)
begin
if (!RESB0)
OUTFF0 <= 0;
else
OUTFF0 <= RESB0;
end
// mux inverted out0
always @ (CK1 or OUTFR0 or OUTFF0)
begin
case (CK1)
0 : OUTMUX0 = ~OUTFR0;
1 : OUTMUX0 = ~OUTFF0;
// default : OUTMUX0 = ~OUTFR0;
endcase
end
// RESB1
assign RESB1 = PORB & SCK1;
// dfrrl1
always @ (posedge CK1 or negedge RESB1)
begin
if (!RESB1)
OUTFR1 <= 0;
else
OUTFR1 <= RESB1;
end
// dffrl1
always @ (negedge CK1 or negedge RESB1)
begin
if (!RESB1)
OUTFF1 <= 0;
else
OUTFF1 <= RESB1;
end
// mux inverted out0
always @ (CK0 or OUTFR1 or OUTFF1)
begin
case (CK0)
0 : OUTMUX1 = ~OUTFR1;
1 : OUTMUX1 = ~OUTFF1;
// default : OUTMUX1 = ~OUTFR1;
endcase
end
// RS
assign RS = ~(OUTMUX0 & SEL);
// SEL
assign SEL = ~(RS & OUTMUX1 & PORB);
// mux out clock
always @ (CK0 or CK1 or SEL)
begin
case (SEL)
0 : CKO = CK0;
1 : CKO = CK1;
// default : CKO = CK1;
endcase
end
endmodule