gates delay in verilog HDL

[Y.T_comp]

hi all :-D
i have new question here:
i was reading in chapter 2 in mano book "digital design 2'end edition "
it was about gates delay in HDL .
he explain as normal this paragraph by an example which is :



AND have 30ns delay ,OR 20ns and NOT 10ns .


and he side that the port X will go to it's final state after tow negatve spike or(20 nsec) .

so dose anyone know why he said that ?why X don't continue in its old state while this 20ns of delay end ?

thank you .

code of example is :

---

Code Verilog - [expand]
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module smplcirct;
    reg A,B,C;
    wire X,y;
 
    simple_circuit_with_delay CWD();
        initial 
        begin
            A=;B=;C=;
            #100
            A=;B=;C=;
            #100 
        $finish;
endmodule   
 
module simple_circuit_with_delay (A,B,C,X,Y);
    input A,B,C;
    output X,Y;
    wire e;
 
    and #(30) G1(e,A,B);
    not #(10) G2(Y,C);
    or #(20) G3(X,e,y);
endmodule;

---

 

[mrflibble]

That "Output of gates after delay" table in the second attachment seems to be plain wrong, given the circuit with delays from your first attachment.. Best just ignore that part of the book and move on. Otherwise you end up looking for clues where none are to be found. Seems the author of the book just made an error, nothing new there...

---------- Post added at 19:49 ---------- Previous post was at 19:48 ----------

Case in point ... when the C input is 0 value, I would expect the inverter output "y" to be 1 value. Which is not the case in that "Output of gates after delay" table...

 

[Y.T_comp]

I'm so sorry mrflibble i had a wrong in the table i updated to the right one i hop that you can help me .

 

[mrflibble]

Alright, just checked the new table and that seems to be correct. So what was the problem again? All I understood from your post was that you didn't understand something.

 

[Y.T_comp]

just this one

why X don't continue in its old state while this 20ns of delay end ?

 

[mrflibble]

You already wrote that in the first post. I didn't understand it then, I don't now. Your use of language is a bit ambiguous (to me). Just try explain it differently, and maybe I get it.

 

[Y.T_comp]

I'm sorry about MY English because IT'S not my native language .

my question is simply the output X - when input '000'- was 1 so when we change the inputs to '111' we have 20n second of delay ... in this case the X must have the same old statue until 20 nsec finish to take the final statue ... so why 2 negative spike take to have the final statue why not positive ?

thank you very much mrflibble because you try to help me :razz:

 

[mrflibble]

Ah okay, I think I get what you mean now.

Well, you have 3 gates ... not just 1. All with a different propagation delay, so you have to work out all the changes in sequence.

Any change on the A and B port will take 20 ns before the change arrives at "e". And after the change arrives at point "e" it will take an ADDITIONAL 20 ns before it will arrive at point. So suppose you make only a change at port A, then it will take a total of 50 ns before the effect of this input reaches the "x" output.

And to make things a little more difficult, you have 3 changes all at once. Now since AB goes from 00 to 11 through an AND gate that makes it a bit easier.

At t=0 changes from AB=00 to AB=11, so at t=30 this reaches the output of the AND gate (point "e").

Similar story for C ...

At t=0 C changes from C=0 to C=1, so at t=10 this reaches the output of the NOT gate (point "y").

You just work out the e, x, y results for every 10 ns step and you'll see what is happening.

Hope that helps.