amny
Newbie level 4
Hello. please help me to solve my problem. I want to run my test bench on gate level Verilog netlist in modelsim. but I am getting the follower error:
#**Error: /home/abbas/Desktop/pomyprfirst/tsmc18.v(7947): $hold( posedge CK:1170 ns, posedge RN:1170 ns, 500 ps );
# Time: 1170 ns Iteration: 1 Instance: /test_tbmpe/uut/c1/\c_reg[0]
# ** Error: /home/abbas/Desktop/pomyprfirst/tsmc18.v(7947): $hold( posedge CK:1170 ns, posedge RN:1170 ns, 500 ps );
# Time: 1170 ns Iteration: 1 Instance: /test_tbmpe/uut/c1/\c_reg[6]
#**Error: /home/abbas/Desktop/pomyprfirst/tsmc18.v(7947): $hold( posedge CK:1170 ns, posedge RN:1170 ns, 500 ps );
# Time: 1170 ns Iteration: 1 Instance: /test_tbmpe/uut/c1/\c_reg[0]
# ** Error: /home/abbas/Desktop/pomyprfirst/tsmc18.v(7947): $hold( posedge CK:1170 ns, posedge RN:1170 ns, 500 ps );
# Time: 1170 ns Iteration: 1 Instance: /test_tbmpe/uut/c1/\c_reg[6]