@ThisIsNotSam As I mentioned in my post, the gate level simulation without SDF works correctly. The problem occurs when I apply the SDF.
@ads-ee I suspected that could be the problem, that's why I mentioned the input/output delays, but I haven't figured how to fix that. I'm using the same test bench for the RTL for the gate level synthesis. All material I've read so far, do not appear to do any adjustments to the test bench for the gate level simulation. Yes, I'm applying reset and clock to the DUT.