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Gate-Level Power Estimation - Synopsys PLI Interface

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anwayy

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Anyone who use Synopsys's PowerCompiler together with VCS to analyze power?
We must install and configure PLI interface first. Two files are needed---- vpower.tab and libvpower.a, right!
I am trying to do this under Linux environment but there's no libvpower.a file for Linux, that means only the file for HPux, Sun and Solaris OS is there. So how can I do it? Someone tell me. Thanks!
 

roli

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Re: Gate Level Power Estimation - Synopsys PLI Interface

Although being VERY VERY late (4 years ...), these Synopsys PLIs can be found in ANY Synopsys DC distribution.

Yes, now there's available!
For example - in Synopsys DC 2004 suite:

./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-aix64/libvpower.a
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-aix64/libvpower.so
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-amd64/libvpower.a
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-amd64/libvpower.so
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-hp32/libvpower.sl
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-hp32/libvpower.a
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-hp64/libvpower.sl
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-hp64/libvpower.a
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-linux/libvpower.a
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-linux/libvpower.so
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-linuxipf/libvpower.a
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-linuxipf/libvpower.so
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-rs6000/libvpower.so.mti
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-rs6000/libvpower.a
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-rs6000/libvpower.so
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-rs6000/libvpower.so.vxl
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-sparc64/libvpower.a
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-sparc64/libvpower.so
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-sparcOS5/libvpower.a
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-sparcOS5/libvpower.so
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/vcs/vcs.sample/vpower.tab


Step-by-step methodology description
(can be done with DC & Simulator ONLY!)
============================

1. With DC (generate SAIF from RTL, and also a synthesized DB):
set power_preserve_rtl_hier_names true
analyze -format verilog {MyDesign.v}
elaborate MyDesign
link
rtl2saif -output MyDesign_fw.saif -design MyDesign
create_clock -name CLK -period 100
uniquify -force
compile -map_effort high
change_names -rules verilog -hierarchy
write -format verilog -hierarchy -output MyDesign_syn.v
write -format db -hierarchy -output MyDesign.db

--

2. With DC (convert synthesized DB file to SAIF):
[ ... read_lib [technology.db] ... ]
lib2saif -output MyDesign.saif MyDesign.db

Note:
In the gate-level methodology using SAIF, the forward-annotation file
is necessary only if you are capturing state- and path-dependent
switching activity. Your technology library must be characterized for
state- and path-dependent (SDPD) power if you want to capture state- and
path-dependent switching activity.

Thus, if your technology library does not include characterization for
state- and path-dependent power, you cannot use 'lib2saif'.

--

3. Link your simulator (for example - NC-Verillog) to Synopsys PLI "libvpower":
ncverilog +ncaccess+r +loadpli1=$SYNOPSYS/auxx/syn/power/vpower/lib-$ARCH/libvpower.so:saifpli_bootstrap
+ncaccess+r [other files]

--

4. With Simulator:
Load these generated SAIF files into your test file, using the "$read_lib_saif" & $read_rtl_saif commands, and generate a Switching Activity SAIF:

Details:
Now after linking, this PLI allows you to perform the following Verilog System Tasks (in your test bench):

//read the library (synthesized design) saif file
$read_lib_saif("MyDesign.saif");

//read the design (RTL converted to saif) saif file
$read_rtl_saif("./MyDesign_fw.saif", "MyDesign_tb.uut");
[
where your "MyDesign_tb.uut" is your DUT instance name under "MyDesign_tb" test bench module. Namely:

module MyDesign_tb;
reg clk;
MyDesign uut ( // design ports ); // DUT instantiation
always #50 clk = !clk;
...
...
endmodule
]

//monitor gates=ON to record toggles
$set_gate_level_monitoring("ON");

//specify part of the design for which toggle info is collected - for entire design use UUT_DESIGN
$set_toggle_region("MyDesign_tb.uut");

//start toggle recording
$toggle_start;

....
stimuli ..
....

//done toggle recording
$toggle_stop;

//write out a backward saif file
$toggle_report("MyDesign_bw.saif", 1.0e-9, "MyDesign_tb.uut");

Now you have the Switching Activity *.saif file for Power Report.

--

5. With DC - report power:
set power_preserve_rtl_hier_names true
read_db MyDesign.db
read_saif -input MyDesign_bw.saif -instance_name MyDesign_tb/uut
report_power


==================================

Note:
I think this issue is important enough to bump it up, even after 4 years ... ...
Because it allows getting Switching Activity from simulator, and then backannotate the *.saif output from simulator to PrimePower, or PowerCompiler, or even DesignCompiler - to get power estimation.
 

win3y

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Thank for posting
W3Y
 

ybhphoenix

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Re: Gate Level Power Estimation - Synopsys PLI Interface

Hi roli,

After another 6 years :) Could you help to find the libvpower or DPFLI for Synopsys DC 2010.03. I have checked "$install path$/auxx/syn", but it is not there.
Does DC2010 still use libvpower or DPFLI.

Thanks a lot.

Although being VERY VERY late (4 years ...), these Synopsys PLIs can be found in ANY Synopsys DC distribution.

Yes, now there's available!
For example - in Synopsys DC 2004 suite:

./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-aix64/libvpower.a
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-aix64/libvpower.so
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-amd64/libvpower.a
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-amd64/libvpower.so
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-hp32/libvpower.sl
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-hp32/libvpower.a
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-hp64/libvpower.sl
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-hp64/libvpower.a
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-linux/libvpower.a
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-linux/libvpower.so
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-linuxipf/libvpower.a
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-linuxipf/libvpower.so
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-rs6000/libvpower.so.mti
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-rs6000/libvpower.a
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-rs6000/libvpower.so
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-rs6000/libvpower.so.vxl
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-sparc64/libvpower.a
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-sparc64/libvpower.so
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-sparcOS5/libvpower.a
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/lib-sparcOS5/libvpower.so
./syn_vV-2004.06-SP2/auxx/syn/power/vpower/vcs/vcs.sample/vpower.tab


Step-by-step methodology description
(can be done with DC & Simulator ONLY!)
============================

1. With DC (generate SAIF from RTL, and also a synthesized DB):
set power_preserve_rtl_hier_names true
analyze -format verilog {MyDesign.v}
elaborate MyDesign
link
rtl2saif -output MyDesign_fw.saif -design MyDesign
create_clock -name CLK -period 100
uniquify -force
compile -map_effort high
change_names -rules verilog -hierarchy
write -format verilog -hierarchy -output MyDesign_syn.v
write -format db -hierarchy -output MyDesign.db

--

2. With DC (convert synthesized DB file to SAIF):
[ ... read_lib [technology.db] ... ]
lib2saif -output MyDesign.saif MyDesign.db

Note:
In the gate-level methodology using SAIF, the forward-annotation file
is necessary only if you are capturing state- and path-dependent
switching activity. Your technology library must be characterized for
state- and path-dependent (SDPD) power if you want to capture state- and
path-dependent switching activity.

Thus, if your technology library does not include characterization for
state- and path-dependent power, you cannot use 'lib2saif'.

--

3. Link your simulator (for example - NC-Verillog) to Synopsys PLI "libvpower":
ncverilog +ncaccess+r +loadpli1=$SYNOPSYS/auxx/syn/power/vpower/lib-$ARCH/libvpower.so:saifpli_bootstrap
+ncaccess+r [other files]

--

4. With Simulator:
Load these generated SAIF files into your test file, using the "$read_lib_saif" & $read_rtl_saif commands, and generate a Switching Activity SAIF:

Details:
Now after linking, this PLI allows you to perform the following Verilog System Tasks (in your test bench):

//read the library (synthesized design) saif file
$read_lib_saif("MyDesign.saif");

//read the design (RTL converted to saif) saif file
$read_rtl_saif("./MyDesign_fw.saif", "MyDesign_tb.uut");
[
where your "MyDesign_tb.uut" is your DUT instance name under "MyDesign_tb" test bench module. Namely:

module MyDesign_tb;
reg clk;
MyDesign uut ( // design ports ); // DUT instantiation
always #50 clk = !clk;
...
...
endmodule
]

//monitor gates=ON to record toggles
$set_gate_level_monitoring("ON");

//specify part of the design for which toggle info is collected - for entire design use UUT_DESIGN
$set_toggle_region("MyDesign_tb.uut");

//start toggle recording
$toggle_start;

....
stimuli ..
....

//done toggle recording
$toggle_stop;

//write out a backward saif file
$toggle_report("MyDesign_bw.saif", 1.0e-9, "MyDesign_tb.uut");

Now you have the Switching Activity *.saif file for Power Report.

--

5. With DC - report power:
set power_preserve_rtl_hier_names true
read_db MyDesign.db
read_saif -input MyDesign_bw.saif -instance_name MyDesign_tb/uut
report_power


==================================

Note:
I think this issue is important enough to bump it up, even after 4 years ... ...
Because it allows getting Switching Activity from simulator, and then backannotate the *.saif output from simulator to PrimePower, or PowerCompiler, or even DesignCompiler - to get power estimation.
 

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