gate length for 45 nm technology

Eman kamel · May 19, 2012

i am choosing design parameter for 45 nm technology NMOS transistor that is a part of interconnect buffer
in ptm model
http://ptm.asu.edu/cgi-bin/test/nanocmos.cgi
the suggested values for transistor width is 17.5 nm

for NangateOpenCellLibrary
http://www.eda.ncsu.edu/wiki/FreePDK45:Contents
the suggested chanel width is 50 nm

which value shall i pick?

thanks in advance
Eman

keith1200rs · May 19, 2012

In your first link it is suggesting 17.5nm Leff which is EFFECTIVE length, not drawn length. You normally design by specifying drawn length. The effective length for a given drawn length will be determined by your technology.

Keith

buckaroo · May 23, 2012

It will impact the reliability, which highly depends on your supply voltage
for 50nm L, VDD~1.3
for 45nm L, VDD~1.2

gate length for 45 nm technology

Eman kamel

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keith1200rs

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buckaroo

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gate length for 45 nm technology

Eman kamel

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