I designed the schematic (picture attached) , and my question is about the pull up resistor R1 when I choose a value of 4MOhms I notice that there is a difference of voltage of 1 V between the supply (4V) and the gate of the PMOS and this difference is reduced when I decrease the value of R1 (0.5 V for 1.5 Mohms), is this due to the leakage current of the gate?? is that normal? I think that the gate current is very low and I should have the same voltage (4 V)at the gate!!!!!
Are you taking into account the current flowing in to the volt meter itself?
It is unusual to configure a MOSFET circuit like that, the resistor is a 'pull down' and the switch connects the gate to ground to turn the MOSFET on. Is that what you intended?
There will be some leakage into the gate as well, it will be very small but 4M limits the possible current to only 0.1uA even when the switch is closed.
The meter itself is drawing current and pulling the voltage down. Think of it like a potential divider with the physical resistor at the top and the internal resistance of the meter at the bottom. What you are seeing is the voltage at the middle. Most DMM have around 10M input resistance and your oscilloscope input attenuator is probably around the same so you create a potential divider with 4M at the top and 10M at the bottom.
The meter itself is drawing current and pulling the voltage down. Think of it like a potential divider with the physical resistor at the top and the internal resistance of the meter at the bottom. What you are seeing is the voltage at the middle. Most DMM have around 10M input resistance and your oscilloscope input attenuator is probably around the same so you create a potential divider with 4M at the top and 10M at the bottom.