Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Look at it carefully, And you will see that when the uC outputs a HIGH, that causes the FET to conduct, which means node 3 is at GND potential. This causes the PNP BJT to conduct while at the same time the NPN BJT dosent conduct because the common emitter would be sitting at 0.7V above the base(node 3 which is GND) of the NPN BJT, hence no conduction will occur for the NPN BJT. With this you can infer that when the uC output is HIGH then the PNP BJT is turned on and the Emitter is switched to LOW. And when uC output is LOW, then the FET is OFF and the NPN conducts because Vbe is positive but PNP BJT dosent conduct because it cant sink any current. Hence the common emitter sits at Vcc (technically a diode drop should be accounted for as well).
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.