Hi,
Thanks for your reply.
Im looking for the methology of gate calculation / or do have any standard libaray for it?
Example with an HDL code as below with a Macros function ADD,
architecture ADDER of A_design is
begin
ASYNCHRONOUS_State0_SM : process (A,b,c)
begin
X <= "00";
X <= ADD (A,b,c);
end process ASYNCHRONOUS_State0_SM;
end ADDER;
then im intrested to know what is the actual gate will be systhesis? and if the design go more comple, what is the logic gate / register will be systhesis...
Best Regards,
syhsim