Contacting both ends reduces Rg if the two ends are
strapped by common metal. I would not route through
a gate segment unless it was within the boundaries of
a single low level cell (like, standard cell library DFF
would suffer if forced to use M1 and above only, and
can probably stand some greater than ideal resistance
in the internal routing).
If you run current through the gate stripe then you may
see longitudinal debiasing effects, DC or transient. This
will not be modeled most likely. So don't, or overstrap
with metal.
RF CMOS designers almost always contact both ends
of the gate.