Gate-charge simulation in hspice

[cmos80]

Could someone please help me with the gate-charge simulation netlist?

Trying to use 2 fixed current source ig & id but I encountered 2 problems:
1) vd vs charge, vd rises initally before decreases as expected
2) vg does not level at maxVg=6V

Thank you in advance!

******* QG Simulation ***********

.OPTION post nomod ingold=2
.param ig=50p maxVg=6
.param id=1m maxVd=30

mn1 d g s b nmos1 w=10u l=1.5u m=100

iscr1 0 g1 pwl 0 0 0.001 ig
iscr2 vdd d id
vda vdd 0 maxVd
vga g g1 maxVg
vss s 0 0
vbb b 0 0

.ic V(d)=maxVd V(g)=0
.tran 0.01 1
.print vd=par('v(d)') vg=par('v(g)') id=par('id') ig=par('ig')

.model nmos1 nmos level=49
.end

 

[dick_freebird]

You're not going to get a meaningful gate charge result,
when you have no parameters at all on the MOSFET model
(particularly cgb, cgd and cgs related ones).

 

[cmos80]

In this simulation, the key is the gate capacitance which is defined by the tox and tox has a default value. So, i don't think this is the reason for the simulation not running correctly.

Is there any kind soul can debug my netlist? thank you!

 

[cmos80]

basically, i want the voltage to stop climbing when it reached maximum vg value to match my measurement data.

any method to achieve this?

Pls help!! thanks!