Gain of cmos inverter

[GagarinMolotov]

Does anybody know how increasing / decreasing in Vdd affects gain of the cmos inverter(Wp = 2Wmin W n = 1Wmin) ? It is pretty hard nut to *****

 

[Audioguru]

RCA invented Cmos logic a long time ago. They published the gain and high frequency response of an inverter (CD4069) at different supply voltages.
I think the responses of a CD4049 will be different.
A 74C04 is the same as a CD4069.

 

[LvW]

Does anybody know how increasing / decreasing in Vdd affects gain of the cmos inverter(Wp = 2Wmin W n = 1Wmin) ? It is pretty hard nut to *****

To me, it is not quite clear what you really want to know.
Do you need information on CMOS inverters that are used as LINEAR amplifiers?

 

[GagarinMolotov]

RCA invented Cmos logic a long time ago. They published the gain and high frequency response of an inverter (CD4069) at different supply voltages.
I think the responses of a CD4049 will be different.
A 74C04 is the same as a CD4069.

I mean in general, if we take to consideration an inverter from the book (Weste and Harris),maybe show some equations

 

[Audioguru]

I mean in general, if we take to consideration an inverter from the book (Weste and Harris),maybe show some equations

I don't know your book and I don't know which Cmos logic inverter is talked about in it. Maybe the inverter is not available and is just make-believe.
Ask a semiconductor manufacturer to make a few thousand like the one in your book then you can measure them all and form your own equations.
It sounds like a useless school assignment.

 

[ninju]

Refer Rabaey, your question is answered in that book. (reducing Vdd increases gain upto a certain voltage)

 

[Audioguru]

With a higher supply voltage, the complementary Mosfets conduct more current which loads them and reduces the voltage gain.

 

[Kenneth_Potter]

Hello everyone,

If I may propose the following. If we assume that both the NMOS and PMOS transistors are held in saturation and that the output voltage is 0.5*Vdd if we let Vgs-Vt = 0.2 then gm=10*Ids.

Maximum gain is Av=gm*(Rp||Rn)=5Vdd

This implies gain increases with supply voltage.

Any thoughts on this?

 

[Audioguru]

A complementary Cmos inverter is a class-A amplifier. When the supply voltage is increased then the idle current increases so the Mosfets are loading each other more and more which reduces the voltage gain.