Cypress FX3 Watermark calculation
Hi,
does anyone know how to calculate the FX3 Watermark?
My current approach is to set a number and look in the oscilloscope how many cycles I have to count down in the FPGA.
My current setup:
8 bit bus from my FPGA to the cypress FX3
https://www.cypress.com/file/136056/download
Page 17 (8.3 General Formulae for Using Partial Flags)
1. When writing from an external master to the synchronous Slave FIFO:
(a) The number of data words that may be written after the clock edge at which the partial flag is sampled low =
watermark x (32/bus width) – 4
The watermark is set to 2 in the Firmware for 4 Sockets
The watermark flag is set to Current_thread_DMA_Watermark in the GPIF2 Designer
The Bus width is 8
2*(32/8)-4=4
I would expect that the watermark is asserted 4 cycles before the buffer is full (maybe +2 according to page 13)
But practically I have to count 30 cycles until the buffer is really full, what am I doing wrong? Does anyone know how to calculate the Cypress FX3 Watermark?
30 cycles give me the correct result from the FPGA to the FX3.