Functions in VHDL Test bench

[hithesh123]

I have repeated code blocks in my test bench.
what is the C equivalent of function in vhdl testbench to generate repeated code.

 

[shahulakthar]

Hi hithesh
check the link

http://vhdlguru.blogspot.in/2010/03/usage-of-packages-and-functions.html



Also you have option to use portmap technique.

 

[K-J]

I have repeated code blocks in my test bench.
what is the C equivalent of function in vhdl testbench to generate repeated code.

- If you have repeated code blocks, then you should write it once using a VHDL procedure. Then in the places where you currently have the repeated code blocks, you simply call that procedure.
- If your repeated code blocks are not exactly identical, then your procedure likely needs to be parameterized in some fashion to manage those not exactly identical things.
- If your repeated code blocks are all within one process in your testbench, then if you define the procedure within the scope of the process, the procedure can be written very succinctly without having to pass in and out the various signals that you are affecting. An example of this is

architecture rtl of my_entity is
    signal Address_signal:    std_ulogic_vector(15 downto 0);
    signal Data_signal:       std_ulogic_vector(15 downto 0);
    signal Write_signal:      std_ulogic;
    signal Ready_signal:      std_ulogic;
    signal Clock:             std_ulogic;

    -- Note: The procedure 'Write' could also be defined here.  However,
    --       if you did this, then you would also have to list all of the
    --       signals that are used within the procedure as ports to the
    --       procedure.  Many times though only a single process needs to
    --       drive these signals so the procedure can be defined within the
    --       scope of the process in which case those signals can be assigned
    --       or used without having them listed on the interface to that 
    --       procedure as will be demonstrated below.
begin
process Main is
    procedure Write(Addr, Data: std_ulogic_vector) is
    begin
       Address_signal <= Addr;
       Data_signal <= Data;
       Write_signal <= '1';
       wait until (Ready_signal = '1') and rising_edge(Clock);
       Write_signal <= '0';
    end procedure Write;
begin
    Write(x"1234", x"5678"); -- Write '5678' to address '1234'
    ....
end process Main;
end rtl;