ravi123 said:
i wnat to do cross coverage of two 16 bit vectors but I want to exclude some conditions. Is it possible using psl? please provide me some reference.
thanx
Hi,
Not exactly - PSL is a temporal language and does support functional coverage of temporals, what you are looking for is more of a "combinatorial" problem to solve and SystemVerilog's covergroup fit the bill perfectly here, a very simple example (refer to LRM for more complex, useful ones):
covergroup cross_cov @(sample_ev);
coverpoint uart_direction; // TX or RX
coverpoint baud_rate { bins br [] = {100,200,5000} }; // numbers don't necessarily represent true values here
cross cc uart_direction, baud_rate;
endgroup : cross_cov
There is lot more - bins, binsof, ignore, illegal etc.
If you are familiar with VERA or E, this will look similar to you.
BTW - if you use SVA, the temporal part can be defined by SVA and cross coverage by SV.
HTH
Aji
http://www.noveldv.com