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functional coverage using psl

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ravi123

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cross coverage using psl

i wnat to do cross coverage of two 16 bit vectors but I want to exclude some conditions. Is it possible using psl? please provide me some reference.
thanx
 

Yes, you can. in fact you do not need to
you can refer to the topic next to this
 

you can look at some material of psl for help.
 

ravi123 said:
i wnat to do cross coverage of two 16 bit vectors but I want to exclude some conditions. Is it possible using psl? please provide me some reference.
thanx
Hi,
Not exactly - PSL is a temporal language and does support functional coverage of temporals, what you are looking for is more of a "combinatorial" problem to solve and SystemVerilog's covergroup fit the bill perfectly here, a very simple example (refer to LRM for more complex, useful ones):

covergroup cross_cov @(sample_ev);
coverpoint uart_direction; // TX or RX
coverpoint baud_rate { bins br [] = {100,200,5000} }; // numbers don't necessarily represent true values here

cross cc uart_direction, baud_rate;
endgroup : cross_cov

There is lot more - bins, binsof, ignore, illegal etc.

If you are familiar with VERA or E, this will look similar to you.

BTW - if you use SVA, the temporal part can be defined by SVA and cross coverage by SV.

HTH
Aji
http://www.noveldv.com
 

just a correction, psl DO support functional coverage, plese refer to the latest IUS document about abv
 

Arnold said:
just a correction, psl DO support functional coverage, plese refer to the latest IUS document about abv

Not sure if this was a correction to my post - after re-reading my post, I realized perhaps I've conveyed a slightly different message than intended. Sorry about that. PSL DOES support functional coverage, but DOES NOT support a truly "cross coverage". Anyway PSL is not intended to be a coverage language, rather a temporal language, it does have "cover" directive to collect functional coverage but as I mentioned it is some what limited and powerful in its own sense.

Aji
http://www.noveldv.com
 

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