Functional coverage in system verilog VMM

[shashi003]

Hi,

I'm a beginner doing functional coverage using system verilog. I'm having trouble creating a covergroup, that can be used multiple times. The scenario is: there's port_mode which can take 3 values (0,1,2). there are 4 ports, each can take speed values 0,1,2,3,4,5,6. There can be many possible combinations like, port_mode(0,1,2),port0(0,1,2,3,4,5,6),port1(0:6),port2(0:6),port3(0:6).
For this, I have:
class fn_cov;
bit [1:0] port_mode;
bit [2:0] port0_speed, port1_speed, port2_speed, port3_speed
covergroup cg;
PM: coverpoint port_mode { bins mode_0 = {0}; bins mode_1={1}; bins mode_2={2}; }
P0: coverpoint port0_speed;
P1: coverpoint port1_speed;
P2: coverpoint port2_speed;
P3: coverpoint port3_speed;

cross PM, P0, P1, P2, P3;
endgroup

The problem is: PM is set at the start of the test and remains the same through out the test, and P0,P1,P2,P3 can arrive at any point of time. so, for cross to work between PM,P1,P2,P3,P4...i need to sample PM when any one of P0,P1,P2,P3 takes a value. This creates a problem for me, as in the report it shows PM being hit many times, say "x" whereas i expect it to b hit only once(at the start of the test).

How do I make sure that PM is hit only once (ie when it actually gets a value) and at the same time make sure cross gets sampled as well?

Thanks,
Shashi

 

[dave_59]

Why it it a problem to "hit" PM many times with the same value? It does not effect the coverage calculation as long as the .at_least option is set to 1 (the default)