Yes I consulted textbook Behzad Razavi also. I am designing the circuit for small powered devices in cadence gpdk180. I want to know the optimal assumptions for the circuit.
I assumed the design parameters as
1) Vdd = 1.8V
2) Power = 54uW (I comes out to be 30u)
3) SR = 10V/usec
4) Load cap = 2pF
5) GB = 20MHz
6) ICMR- = 0.8V
7) ICMR+ = 1.6V
Help me assuming the optimium overdrive voltages. I have taken circuit from Behzad Razavi p 302
here i have designed nmos input folded cascode transistor. problem is that the pmos transistors and last two nmos tx in cascode structure are working in region 2 i.e triode region. also for biasing i have set v3 and v4 as 880mv and 770mv.
Suggest me some changes for making all transistor working in saturation