Fully differential Folded Cascode op amp bias with PMOS Inputs

[sherlock176]

Please help me in designing the folded cascode amplifier using PMOS inputs

 

[t4_v]

Have you tried searching the net?

Here you'll fing the schematic: https://www.quora.com/What-is-the-output-impedance-of-a-folded-cascode-with-NMOS-input .

 

[sherlock176]

Yes I consulted textbook Behzad Razavi also. I am designing the circuit for small powered devices in cadence gpdk180. I want to know the optimal assumptions for the circuit.

I assumed the design parameters as
1) Vdd = 1.8V
2) Power = 54uW (I comes out to be 30u)
3) SR = 10V/usec
4) Load cap = 2pF
5) GB = 20MHz
6) ICMR- = 0.8V
7) ICMR+ = 1.6V

Help me assuming the optimium overdrive voltages. I have taken circuit from Behzad Razavi p 302

 

[Dominik Przyborowski]

SR=Itail/Cload -> Itail = 20uA
GBW=20 MHz -> gm = 2PI GBW Cload = 250uS -> Itail > 16uA (depends to inversion coefficient of your input mosfets)

 

[sherlock176]

here i have designed nmos input folded cascode transistor. problem is that the pmos transistors and last two nmos tx in cascode structure are working in region 2 i.e triode region. also for biasing i have set v3 and v4 as 880mv and 770mv.

Suggest me some changes for making all transistor working in saturation

 

[Dominik Przyborowski]

bias all transitors by proper cascode current mirrors. An appropriate circuit You can find in any text book

 

[sherlock176]

I have tuned the circuit. I obtained all transistors in saturation region. Now i am faciing one problem.

Gain is coming out to be 52dB and UGB is only 6.7Mhz.
It should be atleast 20MHz and >70dB

How to approach for that?