Wow, hold on! Why are you using all those "after" statements?
You can't use "after ...." in real VHDL development for implementation in your FPGA or CPLD. There is no "logic" to make an "after..." statement.
The after statements are used in your test bench for simulation your logic!
Also I am not sure if your code is alright. Instead I would recommend you to use this code:
Code:
library ieee;
use ieee.std_logic_1164.all;
entity fullAdder is
Port(
a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
cout : out std_logic);
end fullAdder;
architecture arch of fullAdder is
signal aXorB : std_logic;
begin
aXorB <= a xor b;
s <= aXorB xor cin;
cout <= (a and b) or (cin and aXorB);
end arch;
Borrowed from
**broken link removed** which has a good explanation too.